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NetLogic Microsystems, Inc. [NASDAQ: NETL] is constantly seeking qualified, dedicated and motivated individuals looking for their next career challenge. We offer competitive benefits and stock options!
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Job 204 
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Senior Digital Design and Verification Engineer
Description:
Digital design of CMOS networking microchips, specializing in but not limited to Ethenet-based communications. Responsibilities include : Architecture definition of major digital modules within the microchip; Analysis and design of interface contracts between digital and analog circuits, including the design of digital algorithmic solutions for calibrating analog circuits; Design of digital circuits using the Verilog hardware description language; Pre-silicon verification using Verilog, Perl and other suitable tools; Post-silicon validation using high speed sampling scopes and other suitable tools in the lab; System-level debug and application support, including proposing specific solutions to meet customer needs. Proficiency in FPGA design, micro-controller architecture, micro assembler design, embedded firmware development, communications coding techniques, analog circuits and signal integrity, Verilog HDL, PERL Scripting language and HSPICE.
Requirements:
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Job 203
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Senior Signal Integrity and Systems Engineer
Description:
Development of very high speed Integrated Circuits for networking applications using design and debug skills. Model and simulate high speed interconnects using MatLab programming language, write FPGA codes for system level testing and debugging, develop device firmware using micro-controller programming. Design high speed PCBs from schematic entry to circuit simulation; oversee PCB layout by layout engineer; coordinate PCB fabrication with outside vendor. Characterize high spped CMOS devices using state of the art test equipment and documentation results.
Requirements:
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Job 202
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Senior RTL Verification Engineer
Description:
Logic Design Analysis, synthesis, RTL coding. Run Timing-optimization and re-synthesis to meet timing/area contraints. Specify Timing constraints for the blocks based on latency requirements. Mentoring junior engineers for design verification and test. Provide regression cases to verify specific paths in RTL. Participate in the full chip functional and Timing Verification. Proficiency in PrimeTime and design compiler.
Requirements:
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Job 201
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Senior Circuit Verification Engineer
Description:
Circuit design analysis, including functional timing analysis. Critical path analysis and full chip transistor level verification which requires post-silicon timing and functional debug. Mentor junior designers in behavior model simulation and test vector/bench generation. Physical layout floor-planning and post layout extraction/back-annotation. Assist in the transfer of products into manufacturing. Proficiency in INNOLOGIC-BV, HSIM and HSPICE.
Requirements:
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| Job 142
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Analog/Mixed-Signal Design Engineer
Description:
Transistor-level design and layout of high-performance, low-power analog and digital circuits.
Investigate architectures and circuits for high-speed data communication.
Laboratory characterization and debug of prototype and production ICs.
Work with marketing to define product features and specifications.
Work with applications engineering and sales to support customer design-in efforts.
Work with manufacturing to develop test programs for new mixed-signal ICs. Investigate production yield limitations for new products.
Requirements:
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MS or PhD in Electrical Engineering or equivalent experience.
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Basic knowledge of circuit topologies for amplifiers, comparators, data converters (A/D and D/A), and phase-locked loops.
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Theoretical understanding of the design and stabilization of analog and digital feedback loops.
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Experience in laboratory characterization of high-speed analog and mixed-signal devices.
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Ability to work in highly-collaborative teams consisting of circuit designers, mask designers, logic designers, signal-integrity, verification, and test engineers.
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Knowledge of submicron CMOS design issues is desirable.
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| Job 141
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Digital Design/Verification Engineer
Description:
Digital design using Verilog HDL for synthesis and for behavioral modeling of analog submodules.
Develop and maintain top level test plans, full-chip verification suite and associated automation scripts.
Drive efforts to improve design flow, verification methodology, code coverage and DFT.
Requirements:
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MS in EE/CS or equivalent experience.
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Proficiency in Verilog, Perl and Shell Scripting
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Familiarity with building reusable, self-checking test benches
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Self-sufficiency in debugging RTL designs and ability to work closely with others
Desirable Attributes:
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Experience with formal verification tools and constrained-random verification techniques.
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Experience with FPGA design, synthesis / place & route tools and familiarity with DSP concepts.
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Basic knowledge of analog circuit topologies for amplifiers, comparators, data converters (A/D and D/A), and phase-locked loops, and an appreciation for timing issues.
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Self driven, highly motivated personality with a can-do attitude.
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| Job 138
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Senior Verification Engineer
Description:
As Senior Verification Engineer, this person will be responsible for developing and maintaining test plans, verification environments, creating and executing tests and regression strategies, and debugging for multi-million gate ASIC and FPGA. Experience with bus protocols such as PCIe is a plus. Effective communication skills and a strong teamwork approach a must with desire to work in a fast-paced environment.
Requirements:
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MSEE with 5+ years of ASIC and FPGA verification experience.
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Having verified 2 or more high speed, high gate count ASIC or FPGA, which have been transferred to production.
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Fluent in C/C++, Verilog, and PERL.
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| Job 135
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Senior Sofware Engineer
Description:
We are looking for an experienced software developer for designing, implementing and delivering sophisticated networking software that implements heuristics and algorithms for high speed packet processing with integrated chips. The person should have a strong algorithmic background and should be proficient in C/C++, shell scripting, and conversant with developing large amounts of software.
Requirements:
- MS/PhD EE/CS with 6+ yrs of experience,
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- BS/B.Tech/BE with 6-8 yrs of experience.
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| Job 129
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ASIC/Verfication Design Engineer
Description:
Assist Senior ASIC Design Engineers on new product development. Work closely with Senior ASIC Design Engineers and System Architects to specify the interface and control logic for network processor and switch/router and other co-processor devices. Work under the direct supervision of Senior Engineers and assist in implementing the design and verify the functionality and performance of these FPGA and ASIC interface/control devices. Assist senior engineers in testing and debugging the design systems. All work shall be executed under the direct supervision of a Senior Engineer.
Requirements:
- Bachelor's degree or equivalent in Computer Science, Electrical or Electronics Engineering, Computer Engineering or related field.
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Benefits |
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NetLogic Microsystems offers a competitive benefits package with several options for full-time regular employees. Our flexible benefits package allows you to select the benefits that are right for you.
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- Medical insurance
(2 options provided) - Dental insurance
- Life and accidental death and disability insurance
- Long term disability insurance
- 401K retirement plan
- Stock option plan
- Educational assistance program
- Personal time off
- Paid Holidays
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